The present disclosure relates to booster circuits.
In recent years, for flash memories, which are a type of non-volatile storage devices, there has been a demand for data read operation and data rewrite operation which are performed with a single power supply voltage or low power supply voltages. To meet the demand, an on-chip booster circuit may be required which supplies a positive or negative boosted voltage when each operation is performed.
The booster circuit is also becoming a key technology to ensure an operating margin of a non-volatile storage device or an analog circuit in a CMOS process.
FIG. 14 shows a configuration of a conventional booster circuit (see, for example, U.S. Pat. No. 7,176,746). The booster circuit 900 performs boosting operation in accordance with two input clock signals CLK1 and CLK2 having different phases. Reference characters 901a-901e each indicate a charge transfer cell which transfers charge from the preceding stage to the succeeding stage, and reference characters 902a-902d each indicate a boosting capacitor which boosts the output of a charge transfer cell.
FIG. 15 is a diagram showing details of the charge transfer cells 901a-901e. A reference character 903 indicates a charge transfer transistor. Reference characters 904 and 905 indicate switching transistors provided in each of the charge transfer cells 901a-901e, which switch between the input voltage of a charge transfer cell in the preceding stage and the output voltage of the each charge transfer cell, depending on an input to the each charge transfer cell.
Next, operation of the booster circuit 900 of FIG. 14 will be briefly described with reference to FIG. 16.
Initially, at time T1, the clock signal CLK1 transitions from low to high, so that the voltages of the boosting capacitors 902a and 902c are boosted. As a result, the voltages of the output terminals OUT of the charge transfer cells 901a and 901c are boosted, so that the switching transistors 905 of the charge transfer cells 901a and 901c transition to the conductive state, and therefore, the charge transfer transistors 903 are set to the non-conductive state. At the same time, the switching transistors 904 of the charge transfer cells 901b and 901d transition to the conductive state, and therefore, the charge transfer transistors 903 transition to the conductive state. By the aforementioned operation, charge on the output terminals having the boosted voltages of the charge transfer cells 901a and 901c is transferred to the output terminals of the charge transfer cells 901b and 901d. 
At time T2 (a period of time Ttrans after time T1), the clock signal CLK2 transitions from low to high, so that the voltages of the boosting capacitors 902b and 902d are boosted. As a result, the voltages of the output terminals OUT of the charge transfer cells 901b and 901d are boosted, so that the switching transistors 905 of the charge transfer cells 901b and 901d transition to the conductive state, and therefore, the charge transfer transistors 903 are set to the non-conductive state. At the same time, the switching transistors 904 of the charge transfer cells 901c and 901e transition to the conductive state, and therefore, the charge transfer transistors 903 transition to the conductive state. By the aforementioned operation, charge on the output terminals having the boosted voltages of the charge transfer cells 901b and 901d is transferred to the output terminal of the charge transfer cell 901c and the output terminal of the booster circuit 900.
Thereafter, at time T3, boosting operation similar to that which is performed at time T1 is repeated.